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<a href="#define-members">Macros</a>  </div>
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<div class="title">xtmrctr_l.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:gaba99b973ef1f13bf0a2716cf52ca5319"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gaba99b973ef1f13bf0a2716cf52ca5319">XTC_DEVICE_TIMER_COUNT</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:gaba99b973ef1f13bf0a2716cf52ca5319"><td class="mdescLeft">&#160;</td><td class="mdescRight">Defines the number of timer counters within a single hardware device.  <a href="group__tmrctr__v4__0.html#gaba99b973ef1f13bf0a2716cf52ca5319">More...</a><br /></td></tr>
<tr class="separator:gaba99b973ef1f13bf0a2716cf52ca5319"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaea427162ce7e92fd08afb7ee1cc1c12e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>(BaseAddress,  TmrCtrNumber,  RegOffset)</td></tr>
<tr class="memdesc:gaea427162ce7e92fd08afb7ee1cc1c12e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read one of the timer counter registers.  <a href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">More...</a><br /></td></tr>
<tr class="separator:gaea427162ce7e92fd08afb7ee1cc1c12e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga56d9c2d54afce39c3693356e3892547f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">XTmrCtr_WriteReg</a>(BaseAddress,  TmrCtrNumber,  RegOffset,  ValueToWrite)</td></tr>
<tr class="memdesc:ga56d9c2d54afce39c3693356e3892547f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write a specified value to a register of a timer counter.  <a href="group__tmrctr__v4__0.html#ga56d9c2d54afce39c3693356e3892547f">More...</a><br /></td></tr>
<tr class="separator:ga56d9c2d54afce39c3693356e3892547f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga74c246c9f5ac5fb8793f0f792bc8fa0e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga74c246c9f5ac5fb8793f0f792bc8fa0e">XTmrCtr_SetControlStatusReg</a>(BaseAddress,  TmrCtrNumber,  RegisterValue)</td></tr>
<tr class="memdesc:ga74c246c9f5ac5fb8793f0f792bc8fa0e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the Control Status Register of a timer counter to the specified value.  <a href="group__tmrctr__v4__0.html#ga74c246c9f5ac5fb8793f0f792bc8fa0e">More...</a><br /></td></tr>
<tr class="separator:ga74c246c9f5ac5fb8793f0f792bc8fa0e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga45ca70c55615831432d0a2b32e0e77af"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga45ca70c55615831432d0a2b32e0e77af">XTmrCtr_GetControlStatusReg</a>(BaseAddress,  TmrCtrNumber)&#160;&#160;&#160;<a class="el" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>((BaseAddress), (TmrCtrNumber), <a class="el" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>)</td></tr>
<tr class="memdesc:ga45ca70c55615831432d0a2b32e0e77af"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the Control Status Register of a timer counter.  <a href="group__tmrctr__v4__0.html#ga45ca70c55615831432d0a2b32e0e77af">More...</a><br /></td></tr>
<tr class="separator:ga45ca70c55615831432d0a2b32e0e77af"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa6ab051d2011676e6cc3ea8fbc4ec6da"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gaa6ab051d2011676e6cc3ea8fbc4ec6da">XTmrCtr_GetTimerCounterReg</a>(BaseAddress,  TmrCtrNumber)&#160;&#160;&#160;<a class="el" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>((BaseAddress), (TmrCtrNumber), <a class="el" href="group__tmrctr__v4__0.html#gad054cd3c12bc686f9be366e093c2f97a">XTC_TCR_OFFSET</a>) \</td></tr>
<tr class="memdesc:gaa6ab051d2011676e6cc3ea8fbc4ec6da"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the Timer Counter Register of a timer counter.  <a href="group__tmrctr__v4__0.html#gaa6ab051d2011676e6cc3ea8fbc4ec6da">More...</a><br /></td></tr>
<tr class="separator:gaa6ab051d2011676e6cc3ea8fbc4ec6da"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga66eee1751bc9d207eef8143492669c96"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga66eee1751bc9d207eef8143492669c96">XTmrCtr_SetLoadReg</a>(BaseAddress,  TmrCtrNumber,  RegisterValue)</td></tr>
<tr class="memdesc:ga66eee1751bc9d207eef8143492669c96"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the Load Register of a timer counter to the specified value.  <a href="group__tmrctr__v4__0.html#ga66eee1751bc9d207eef8143492669c96">More...</a><br /></td></tr>
<tr class="separator:ga66eee1751bc9d207eef8143492669c96"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga248be00d1ff730871bf8201143dc1480"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga248be00d1ff730871bf8201143dc1480">XTmrCtr_GetLoadReg</a>(BaseAddress,  TmrCtrNumber)&#160;&#160;&#160;<a class="el" href="group__tmrctr__v4__0.html#gaea427162ce7e92fd08afb7ee1cc1c12e">XTmrCtr_ReadReg</a>((BaseAddress), (TmrCtrNumber), <a class="el" href="group__tmrctr__v4__0.html#ga38a380fdcb3114c3db51524a8182c4ad">XTC_TLR_OFFSET</a>)</td></tr>
<tr class="memdesc:ga248be00d1ff730871bf8201143dc1480"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the Load Register of a timer counter.  <a href="group__tmrctr__v4__0.html#ga248be00d1ff730871bf8201143dc1480">More...</a><br /></td></tr>
<tr class="separator:ga248be00d1ff730871bf8201143dc1480"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad1f98a1af5b68454aead939a5a727ff1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gad1f98a1af5b68454aead939a5a727ff1">XTmrCtr_Enable</a>(BaseAddress,  TmrCtrNumber)</td></tr>
<tr class="memdesc:gad1f98a1af5b68454aead939a5a727ff1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable a timer counter such that it starts running.  <a href="group__tmrctr__v4__0.html#gad1f98a1af5b68454aead939a5a727ff1">More...</a><br /></td></tr>
<tr class="separator:gad1f98a1af5b68454aead939a5a727ff1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae5874bbf23d48004ab15acd250a34688"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gae5874bbf23d48004ab15acd250a34688">XTmrCtr_Disable</a>(BaseAddress,  TmrCtrNumber)</td></tr>
<tr class="memdesc:gae5874bbf23d48004ab15acd250a34688"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable a timer counter such that it stops running.  <a href="group__tmrctr__v4__0.html#gae5874bbf23d48004ab15acd250a34688">More...</a><br /></td></tr>
<tr class="separator:gae5874bbf23d48004ab15acd250a34688"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2b0b144df40ea454cd791aa2fbdaeb94"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga2b0b144df40ea454cd791aa2fbdaeb94">XTmrCtr_EnableIntr</a>(BaseAddress,  TmrCtrNumber)</td></tr>
<tr class="memdesc:ga2b0b144df40ea454cd791aa2fbdaeb94"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the interrupt for a timer counter.  <a href="group__tmrctr__v4__0.html#ga2b0b144df40ea454cd791aa2fbdaeb94">More...</a><br /></td></tr>
<tr class="separator:ga2b0b144df40ea454cd791aa2fbdaeb94"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga582e5bbde5675a5750d3e4328493e318"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga582e5bbde5675a5750d3e4328493e318">XTmrCtr_DisableIntr</a>(BaseAddress,  TmrCtrNumber)</td></tr>
<tr class="memdesc:ga582e5bbde5675a5750d3e4328493e318"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the interrupt for a timer counter.  <a href="group__tmrctr__v4__0.html#ga582e5bbde5675a5750d3e4328493e318">More...</a><br /></td></tr>
<tr class="separator:ga582e5bbde5675a5750d3e4328493e318"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga433680f98acc79f69d227a041f20ecb9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga433680f98acc79f69d227a041f20ecb9">XTmrCtr_LoadTimerCounterReg</a>(BaseAddress,  TmrCtrNumber)</td></tr>
<tr class="memdesc:ga433680f98acc79f69d227a041f20ecb9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cause the timer counter to load it's Timer Counter Register with the value in the Load Register.  <a href="group__tmrctr__v4__0.html#ga433680f98acc79f69d227a041f20ecb9">More...</a><br /></td></tr>
<tr class="separator:ga433680f98acc79f69d227a041f20ecb9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac6bbcadfe43a528d4d895650bee25a4e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gac6bbcadfe43a528d4d895650bee25a4e">XTmrCtr_HasEventOccurred</a>(BaseAddress,  TmrCtrNumber)</td></tr>
<tr class="memdesc:gac6bbcadfe43a528d4d895650bee25a4e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Determine if a timer counter event has occurred.  <a href="group__tmrctr__v4__0.html#gac6bbcadfe43a528d4d895650bee25a4e">More...</a><br /></td></tr>
<tr class="separator:gac6bbcadfe43a528d4d895650bee25a4e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register Offset Definitions</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register offsets within a timer counter, there are multiple timer counters within a single device </p>
</div></td></tr>
<tr class="memitem:ga81c9a818cb57cf5f106cf5a3b7c3c59f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">XTC_TCSR_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga81c9a818cb57cf5f106cf5a3b7c3c59f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control/Status register.  <a href="group__tmrctr__v4__0.html#ga81c9a818cb57cf5f106cf5a3b7c3c59f">More...</a><br /></td></tr>
<tr class="separator:ga81c9a818cb57cf5f106cf5a3b7c3c59f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga38a380fdcb3114c3db51524a8182c4ad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga38a380fdcb3114c3db51524a8182c4ad">XTC_TLR_OFFSET</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:ga38a380fdcb3114c3db51524a8182c4ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">Load register.  <a href="group__tmrctr__v4__0.html#ga38a380fdcb3114c3db51524a8182c4ad">More...</a><br /></td></tr>
<tr class="separator:ga38a380fdcb3114c3db51524a8182c4ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad054cd3c12bc686f9be366e093c2f97a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gad054cd3c12bc686f9be366e093c2f97a">XTC_TCR_OFFSET</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:gad054cd3c12bc686f9be366e093c2f97a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timer counter register.  <a href="group__tmrctr__v4__0.html#gad054cd3c12bc686f9be366e093c2f97a">More...</a><br /></td></tr>
<tr class="separator:gad054cd3c12bc686f9be366e093c2f97a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Control Status Register Bit Definitions</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Control Status Register bit masks Used to configure the timer counter device. </p>
</div></td></tr>
<tr class="memitem:gaaf3300005339d29c2ee9a79e6bb81959"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gaaf3300005339d29c2ee9a79e6bb81959">XTC_CSR_CASC_MASK</a>&#160;&#160;&#160;0x00000800</td></tr>
<tr class="memdesc:gaaf3300005339d29c2ee9a79e6bb81959"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cascade Mode.  <a href="group__tmrctr__v4__0.html#gaaf3300005339d29c2ee9a79e6bb81959">More...</a><br /></td></tr>
<tr class="separator:gaaf3300005339d29c2ee9a79e6bb81959"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabfaa1357c7843a1a72c740b017061a38"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gabfaa1357c7843a1a72c740b017061a38">XTC_CSR_ENABLE_ALL_MASK</a>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="memdesc:gabfaa1357c7843a1a72c740b017061a38"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables all timer counters.  <a href="group__tmrctr__v4__0.html#gabfaa1357c7843a1a72c740b017061a38">More...</a><br /></td></tr>
<tr class="separator:gabfaa1357c7843a1a72c740b017061a38"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa6304f96140472ea199517984b5a18d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gaa6304f96140472ea199517984b5a18d5">XTC_CSR_ENABLE_PWM_MASK</a>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="memdesc:gaa6304f96140472ea199517984b5a18d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the Pulse Width Modulation.  <a href="group__tmrctr__v4__0.html#gaa6304f96140472ea199517984b5a18d5">More...</a><br /></td></tr>
<tr class="separator:gaa6304f96140472ea199517984b5a18d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2744df54b0fc4bc5df1dba14a6afc840"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga2744df54b0fc4bc5df1dba14a6afc840">XTC_CSR_INT_OCCURED_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:ga2744df54b0fc4bc5df1dba14a6afc840"><td class="mdescLeft">&#160;</td><td class="mdescRight">If bit is set, an interrupt has occured.  <a href="group__tmrctr__v4__0.html#ga2744df54b0fc4bc5df1dba14a6afc840">More...</a><br /></td></tr>
<tr class="separator:ga2744df54b0fc4bc5df1dba14a6afc840"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa7cbbacf96f3f51bcd12d5826b03e620"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gaa7cbbacf96f3f51bcd12d5826b03e620">XTC_CSR_ENABLE_TMR_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:gaa7cbbacf96f3f51bcd12d5826b03e620"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables only the specific timer.  <a href="group__tmrctr__v4__0.html#gaa7cbbacf96f3f51bcd12d5826b03e620">More...</a><br /></td></tr>
<tr class="separator:gaa7cbbacf96f3f51bcd12d5826b03e620"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0e56ed788d0a3f4b6d89319e03797002"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga0e56ed788d0a3f4b6d89319e03797002">XTC_CSR_ENABLE_INT_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga0e56ed788d0a3f4b6d89319e03797002"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the interrupt output.  <a href="group__tmrctr__v4__0.html#ga0e56ed788d0a3f4b6d89319e03797002">More...</a><br /></td></tr>
<tr class="separator:ga0e56ed788d0a3f4b6d89319e03797002"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa10a23e3e387b53bac89f97cc5adf455"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gaa10a23e3e387b53bac89f97cc5adf455">XTC_CSR_LOAD_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:gaa10a23e3e387b53bac89f97cc5adf455"><td class="mdescLeft">&#160;</td><td class="mdescRight">Loads the timer using the load value provided earlier in the Load Register, XTC_TLR_OFFSET.  <a href="group__tmrctr__v4__0.html#gaa10a23e3e387b53bac89f97cc5adf455">More...</a><br /></td></tr>
<tr class="separator:gaa10a23e3e387b53bac89f97cc5adf455"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab06d844c7a245c7be88a63f3559bbd46"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gab06d844c7a245c7be88a63f3559bbd46">XTC_CSR_AUTO_RELOAD_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:gab06d844c7a245c7be88a63f3559bbd46"><td class="mdescLeft">&#160;</td><td class="mdescRight">In compare mode, configures the timer counter to reload from the Load Register.  <a href="group__tmrctr__v4__0.html#gab06d844c7a245c7be88a63f3559bbd46">More...</a><br /></td></tr>
<tr class="separator:gab06d844c7a245c7be88a63f3559bbd46"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadcf0bfbbe0244d0fc208c783858a9c5c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gadcf0bfbbe0244d0fc208c783858a9c5c">XTC_CSR_EXT_CAPTURE_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:gadcf0bfbbe0244d0fc208c783858a9c5c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the external input to the timer counter.  <a href="group__tmrctr__v4__0.html#gadcf0bfbbe0244d0fc208c783858a9c5c">More...</a><br /></td></tr>
<tr class="separator:gadcf0bfbbe0244d0fc208c783858a9c5c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2345d81184385344ae236b8aa99f2423"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga2345d81184385344ae236b8aa99f2423">XTC_CSR_EXT_GENERATE_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga2345d81184385344ae236b8aa99f2423"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the external generate output for the timer.  <a href="group__tmrctr__v4__0.html#ga2345d81184385344ae236b8aa99f2423">More...</a><br /></td></tr>
<tr class="separator:ga2345d81184385344ae236b8aa99f2423"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6b40b30b1d1d5b07f4101a5b657dddba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#ga6b40b30b1d1d5b07f4101a5b657dddba">XTC_CSR_DOWN_COUNT_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga6b40b30b1d1d5b07f4101a5b657dddba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configures the timer counter to count down from start value, the default is to count up.  <a href="group__tmrctr__v4__0.html#ga6b40b30b1d1d5b07f4101a5b657dddba">More...</a><br /></td></tr>
<tr class="separator:ga6b40b30b1d1d5b07f4101a5b657dddba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa0563f5483d9fef6126df6b2e447da08"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tmrctr__v4__0.html#gaa0563f5483d9fef6126df6b2e447da08">XTC_CSR_CAPTURE_MODE_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gaa0563f5483d9fef6126df6b2e447da08"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the timer to capture the timer counter value when the external capture line is asserted.  <a href="group__tmrctr__v4__0.html#gaa0563f5483d9fef6126df6b2e447da08">More...</a><br /></td></tr>
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